august 1996 ml65244/ML65L244 high speed dual quad buffer/line drivers block diagram general description the ml65244 and ML65L244 are non-inverting dual quad buffer/line drivers. the high operating frequency (50mhz driving a 50pf load) and low propagation delay (ml65244 C 1.7ns, ML65L244 C 2ns) make them ideal for very high speed applications such as processor bus buffering and cache and main memory control. these buffers use a unique analog implementation to eliminate the delays inherent in traditional digital designs. schottky clamps reduce under and overshoot, and special output driver circuits limit ground bounce. the ml65244 and ML65L244 conform to the pinout and functionality of the industry standard fct244 and are intended for applications where propagation delay is critical to the system design. note: this part was previously numbered ml6582. features n low propagation delay 1.7ns ml65244 2.0ns ML65L244 n fast dual 4-bit ttl level buffer/line driver with tri- state capability on the output (two 4-bit sections) n ttl compatible input and output levels n schottky diode clamps on all inputs to handle undershoot and overshoot n onboard schottky diodes minimize noise n reduced output swing of 0 C 4.1 volts n ground bounce controlled outputs, typically less than 400mv n industry standard fct244 type pinout n applications include high speed cache memory, main memory, processor bus buffering, and graphics cards ai yai bi 1g ybi 2g gnd v cc v cc (1 of 4) (1 of 4) rev. 1.0 10/25/2000
ml65244/ML65L244 2 rev. 1.0 10/25/2000 pin configuration top view 20-pin soic, qsop pin description name i/o description ai i data bus a yai o data bus a bi i data bus b ybi o data bus b 1g i output enable for data bus a 2g i output enable for data bus b gnd i signal ground v cc i + 5v supply function table 1g / 2g ai/bi yai/ybi hxz lll lhh 1g a0 yb0 a1 yb1 a2 yb2 a3 yb3 gnd v cc 2g ya0 b0 ya1 b1 ya2 b2 ya3 b3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 absolute maximum ratings v cc ................................................................................ C0.3v to 7v dc input voltage ................................ C0.3 to v cc + 0.3v ac input voltage (< 20ns) ...................................... C3.0v dc output voltage ............................. C0.3 to v cc + 0.3v output sink current (per pin) ............................... 120ma storage temperature ................................ C65c to 150c junction temperature ............................................. 150c thermal impedance ( q ja ) soic ............................................................... 96c/w qsop ............................................................ 100c/w l = logic low h = logic high x = dont care z = high impedance
ml65244/ML65L244 rev. 1.0 10/25/2000 3 electrical characteristics unless otherwise stated, these specifications apply for: v cc = 5.0 5%v, t a = 0c to 70c (note 1). symbol parameter conditions min typ max units ac electrical characteristics (c load = 50pf, r load = 500y) t plh , t phl propagation delay ai to yai, bi to ybi (note 2) ml65244 1.4 1.7 ns ML65L244 1.6 2.0 ns t oe output enable time 10 15 ns 1g , 2g to yai/ybi t od output disable time 10 ns 1g , 2g to yai/ybi c in input capacitance 8 pf dc electrical characteristics (c load = 50pf, r load = ) v ih input high voltage logic high 2.0 v v il input low voltage logic low 0.8 v i ih input high current per pin, v in = 3v ml65244 0.5 1.5 ma ML65L244 0.3 0.5 ma i il input low current per pin, v in = 0 ml65244 2.4 3.5 ma ML65L244 0.8 1.0 ma i hi-z three-state output current v cc = 5.25v, 0 < v in < v cc 5a i os short circuit current v cc = 5.25v, v o = gnd C60 C225 ma (note 3) v ic input clamp voltage v cc = 4.75v, i in = 18ma C0.7 C1.2 v v oh output high voltage v cc = 4.75v, i oh = 100a 2.4 v (notes 4 & 5) v ol output low voltage v cc = 4.75v, i ol = 25ma 0.6 v (notes 4 & 5) v off v in C v out per buffer v cc = 4.75v (note 4) ml65244 0 100 200 mv ML65L244 0 200 300 mv i cc quiescent power v cc = 5.25v, freq = 0hz, 55 80 ma supply current inputs/outputs open note 1: limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. note 2: one line switching, see figure 3, t plh , t phl versus c l . note 3: not more than one output should be shorted for more than a second. note 4: this is a true analog buffer. in the linear region, the output tracks the input with an offset (v off ). for v oh , v in = 2.7v. v oh min includes v off . for v ol , v in = 0v, v ol max includes v off note 5: see figure 2 for i oh versus v oh and i ol versus v ol data. 1.5v 1.5v 1.5v 1.5v t phl t plh t r , t f 4ns 3v 0v 3v 0v input output
ml65244/ML65L244 4 rev. 1.0 10/25/2000 ch1 1.00v ch2 1.00v 10.0ns ch1 1.00v ch2 1.00v 10.0ns +20 0 C20 C40 C60 C80 C100 C120 C140 C160 C180 C200 2.5 i oh (ma) v oh (v) 3.0 3.5 4.0 figure 2a. typical v ol versus i ol for one buffer output. figure 2b. typical v oh versus i oh for one buffer output. 220 200 180 160 140 120 100 80 60 40 20 0 2.5 0.0 i ol (ma) v ol (v) 0.5 1.0 1.5 2.0 3.0 2.5 2.0 1.5 1.0 0.5 0.0 100 30 t pd (ns) load capacitance (pf) 50 75 150 ML65L244 ml65244 210 190 170 150 130 110 90 70 50 10 i cc (ma) frequency (mhz) 20 30 40 50 60 70 80 90 150pf 100pf 75pf 50pf 30pf ml65244 74fct244 figure 1. ground bounce comparison, four outputs switching into 50pf loads. figure 3. propagation delay (t plh , t phl ) versus load capacitance, one output switching. figure 4. i cc versus frequency for various load capacitances, four outputs switching.
ml65244/ML65L244 rev. 1.0 10/25/2000 5 functional description the ml65244 and ML65L244 are very high speed non- inverting buffer/line drivers with three-state outputs which are ideally suited for bus-oriented applications. they provide a low propagation delay by using an analog design approach (a high speed unity gain buffer), as compared to conventional digital approaches. the ml65244 and ML65L244 follow the pinout and functionality of the industry standard fct244 series of buffer/line drivers and are intended to replace them in designs where the propagation delay is a critical part of the system design considerations. the ml65244 and ML65L244 are capable of driving load capacitances several times larger than their input capacitance. they are configured so that the ai inputs go to the yai outputs, with the a side output enable controlled by 1g . similarly, 2g controls the bi inputs which go to the ybi outputs. these unity gain analog buffers achieve low propagation delays by having the output follow the input with a small offset. the output rise and fall times will closely match those of the input waveform. all inputs and outputs have schottky clamp diodes to handle undershoot or overshoot noise suppression in unterminated applications. all outputs have ground bounce suppression (typically < 400mv), high drive output capability with almost immediate response to the input signal, and low output skew. the i ol current drive capability of a buffer/line driver is often interpreted as a measure of its ability to sink current in a dynamic sense. this may be true for cmos buffer/line drivers, but it is not true for the ml65244 and ML65L244. this is because their sink and source current capability depends on the voltage difference between the output and the input. the ml65244 can sink or source more than 100ma to a load when the load is switching due to the fact that during the transition, the difference between the input and output is large. i ol is only significant as a dc specification, and is 25ma. architectural description until now, buffer/line drivers have been implemented in cmos logic and made to be ttl compatible by sizing the input devices appropriately. in order to buffer large capacitances with cmos logic, it is necessary to cascade an even number of inverters, each successive inverter larger than the preceding, eventually leading to an inverter that will drive the required load capacitance at the required frequency. each inverter stage represents an additional delay in the gating process because in order for a single gate to switch, the input must slew more than half of the supply voltage. the best of these cmos buffers has managed to drive a 50pf load capacitance with a delay of 3.2ns. micro linear has produced a dual quad buffer/line driver with a delay less than 1.7ns by using a unique circuit architecture that does not require cascaded logic gates. the ml65244 uses a feedback technique to produce an output that follows the input. if the output voltage is not close to the input, then the feedback circuitry will source or sink enough current to the load capacitance to correct the discrepancy. figure 5. one buffer cell of the ml65244 q1 in out q2 q7 r2 r6 r5 gnd r4 q4 q3 r1 r8 r3 q5 q6 r7 vcc
ml65244/ML65L244 6 rev. 1.0 10/25/2000 the basic architecture of the ml65244 is shown in figure 5. it is implemented on a 1.5m bicmos process. however, in this particular circuit, all of the active devices are npns the fastest devices available in the process. in this circuit, there are two paths to the output. one path sources current to the load capacitance when the signal is asserted, and the other path sinks current from the output when the signal is negated. the assertion path is the emitter follower path consisting of the level shift transistor q1, the output transistor q2, and the bias resistor r8. it sources current to the output through the 75y resistor r7 which is bypassed by another npn (not shown) during fast input transients. the negation path is a current differencing op amp connected in a follower configuration. the active components in this amplifier are transistors q3Cq7. r3Cr6 are bias resistors, and r1 and r2 are the feedback resistors. the key to understanding the operation of the current differencing op amp is to know that the currents in transistors q3 and q5 are the same at all times and that the voltages at the bases of q4 and q6 are roughly the same. if the output is higher than the input, then an error current will flow through r2. this error current will flow into the base of q6 and be multiplied by b squared to the collector of q7, closing the loop. the larger the discrepancy between the output and input, the larger the feedback current, and the harder q7 sinks current from the load capacitor. a number of mosfets are not shown in figure 5. these mosfets are used to three-state dormant buffers. for instance, the feedback resistors r1 and r2 were implemented as resistive transmission gates to ensure that disabled buffers do not load the lines they are connected to. similarly, there is a pmos in series with r8 that is normally on but shuts off for disable. other mosfets have been included to ensure that disabled buffers consume no power. termination r7 in figure 5 also acts as a termination resistor. this 75y resistor is in series with the output and therefore helps suppress noise caused by transmission line effects such as reflections from mismatched impedances. system designers using cmos transceivers commonly have to use external resistors in series with each transceiver output to suppress this noise. systems using the ml65244 or ML65L244 may not have to use these external resistors. applications there are a wide variety of needs for extremely fast buffers in high speed processor system designs like pentium, powerpc, mips, sparc, alpha and other risc processors. these applications are either in the cache memory area or the main memory (dram) area. in addition, fast buffers find applications in high speed graphics and multimedia applications. the high capacitive loading due to multiplexed address lines on the system bus demand external buffers to take up the excess drive current. the needed current to skew the transitions between rise and fall times must be done without adding excessive propagation delay. the ml65244 and ML65L244 are equipped with schottky diodes to clean up ringing from overshoot and undershoot caused by reflections in unterminated board traces.
ml65244/ML65L244 rev. 1.0 10/25/2000 7 physical dimensions inches (millimeters) package: s20w 20-pin soic package: k20 20-pin qsop seating plane 0.291 - 0.301 (7.39 - 7.65) pin 1 id 0.398 - 0.412 (10.11 - 10.47) 0.498 - 0.512 (12.65 - 13.00) 0.012 - 0.020 (0.30 - 0.51) 0.050 bsc (1.27 bsc) 0.022 - 0.042 (0.56 - 1.07) 0.095 - 0.107 (2.41 - 2.72) 0.005 - 0.013 (0.13 - 0.33) 0.090 - 0.094 (2.28 - 2.39) 20 0.007 - 0.015 (0.18 - 0.38) 0o - 8o 1 0.024 - 0.034 (0.61 - 0.86) (4 places) package: s20 20-pin soic pin 1 id seating plane 0.150 - 0.160 (3.81 - 4.06) 0.228 - 0.244 (5.79 - 6.20) 0.338 - 0.348 (8.58 - 8.84) 0.008 - 0.012 (0.20 - 0.31) 0.025 bsc (0.63 bsc) 0.015 - 0.035 (0.38 - 0.89) 0.060 - 0.068 (1.52 - 1.73) 0.004 - 0.010 (0.10 - 0.26) 0.055 - 0.061 (1.40 - 1.55) 0.006 - 0.010 (0.15 - 0.26) 0o - 8o 20 0.050 - 0.055 (1.27 - 1.40) (4 places) 1 package: k20 20-pin qsop
ml65244/ML65L244 8 rev. 1.0 10/25/2000 8/21/96 printed in u.s.a. 2092 concourse drive san jose, ca 95131 tel: 408/433-5200 fax: 408/432-0295 micro linear reserves the right to make changes to any product herein to improve reliability, function or design. micro linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. the circuits contained in this data sheet are offered as possible applications only. micro linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. the customer is urged to consult with appropriate legal counsel before deciding on a particular application. ? micro linear 1996 is a registered trademark of micro linear corporation products described in this document may be covered by one or more of the following patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017. other patents are pending. ordering information part number speed temperature range package ml65244ck 1.7ns 0c to 70c 20-pin qsop (k20) ml65244cs 1.7ns 0c to 70c 20-pin soic (s20) ML65L244ck 2.0ns 0c to 70c 20-pin qsop (k20) ML65L244cs 2.0ns 0c to 70c 20-pin soic (s20) intel, pentium, pci are registered trademarks of intel corporation. mips, alpha and sparc are registered trademarks of silicon graphics, dec and sun microsystems respectively.
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